Many programmable integrated circuits (ICs) are configured to receive and/or transmit a high-speed digital data stream from and to other digital devices in a system along a data channel (“channel”). An ideal incoming digital data stream would have a series of square-wave-type pulses with vertical leading and trailing edges and a flat ideal. However, incoming digital data streams are not perfect. Deviation from ideality can be caused by frequency-dependent attenuation of the channel over which the data is transmitted. For example, if the channel, such as a wire trace on a printed circuit board or transmission line, presents more attenuation at higher frequencies than at lower frequencies, phase distortion of the incoming digital data stream can occur.
Inter-symbol interference (“ISI”) causes bits in a data stream to deviate from ideal. Each bit of incoming data is “stretched” by its adjacent bits and other bits in the data stream. The resultant incoming digital data stream has pulses with sloped leading and trailing edges and rounded corners. For example, the first bit adds a small amount of voltage to the second bit to produce a summed waveform that is unlike either the first or second bit.
At the end of a long serial data communication, such as in systems with serializer/de-serializer (“SERDES”) receivers, the incoming waveform might not look like the waveform that was sent from the data-transmitting device. SERDES receivers are used in programmable ICs, such as field programmable gate arrays (FPGAs). To compensate for these changes in the incoming waveform, equalization is applied to correct the received signal.
SERDES transceivers generally utilize various equalizers to compensate for ISI. One equalization method, known as continuous-time linear equalization (CTLE), utilizes active circuitries to boost the gain at various frequencies and compensate for the channel loss. CTLE provides a hardware and power-efficient solution for equalization. However, linear equalizers amplify all frequencies within the equalizer bandwidth, including cross-talk and ripple. As a result, CTLE does not provide an ideal solution in for high-frequency compensation, which may be subject to various noise sources.
Another equalization method is decision-feedback equalization (“DFE”). DFE applies a selected correction signal (e.g. voltage or current) to an input bit at a summing node that compensates for the frequency-dependent attenuation of the channel carrying the data to the receiver. In some systems, DFE is essentially the inverse function of the channel attenuation as a function of frequency. DFE can equalize with higher immunities against effects from many types of un-wanted signals (cross-talk, reflections, and other general electronic noise), but also increases hardware complexity and power requirements.
When performance, power efficiency, and hardware requirements are considered, different application environments may be better suited to one particular equalization method over the other. Because the ultimate application of a programmable IC is unknown, designers of SERDES for programmable ICs routinely face the challenge of achieving lowest power possible, while keeping the designs flexible so they can address an extremely wide range of applications.
One solution is to implement both types of equalizers on the programmable IC, with some channels using DFE and some channels using CTLE. However, this approach is not optimal because some applications may exhaust a particular type of channel while leaving channels of the other type unused. Using a DFE for applications that can be performed with CTLE wastes power. Conversely, a CTLE channel often cannot serve in an environment that is only meant to be served by DFE.
One or more embodiments of the present invention may address one or more of the above issues.